This Invention relates to the field of data processing systems. More particularly, this invention relates to data processing systems incorporating mechanisms for prefetching from memory.
It is known to provide data processing systems with prefetching mechanisms. Such prefetching mechanisms may include instruction prefetching mechanisms that seek to fetch from a higher level in the memory system program instructions required to execute a desired stream of program instructions in advance of these program instructions being required for execution. A problem is that there may be discontinuities in the stream of program instructions executed due to, for example, branch instructions or return and call instructions. If the prefetching mechanisms fail to supply the program instructions required, then this can stall the processor resulting in a significant loss of performance.
It is known to include prefetching mechanisms which seek to predict branch instructions and the outcomes of branch behaviour. The performance benefit to be achieved with accurate branch prediction, particularly in the case of processors with deep instruction pipelines, is significant and accordingly justifies significant resources to be expended to improve the prediction accuracy. Another type of prediction mechanism is based upon the identification of call and return instructions in the program stream. When a call or return instruction is encountered again, then the target address may be predicted based upon the previous behaviour. Thus, a list of addresses at which previous call or return instructions were encountered may be stored together with the target addresses for those call or return instructions.
Measures which can increase the accuracy of the prefetching predictions such that the processor does not stall while waiting for instructions or data to be fetched are strongly advantageous. Furthermore, increases in prediction accuracy which may be achieved with little additional resources are also advantageous.